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A Novel VLSI Architecture of Hybrid Image Compression Model based on Reversible Blockade Transform
VLSI Discrete Cosine Transform JPEG Hartley transform
2010/2/2
Image compression can improve the performance of
the digital systems by reducing time and cost in image storage
and transmission without significant reduction of the image quality.
Furthermore, the...
A Novel VLSI Architecture of Motion Compensation for Multiple Standards
motion compensation VLSI architecture AVS H.264
2013/7/17
Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264...
Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard
FFSBM Algorithm VLSI Architecture AVS Video Standard
2010/12/16
Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard.
Improved FFSBM Algorithm and Its VLSI Architecture for Variable Block Size Motion Estimation of H.264
FFSBM Algorithm VLSI Architecture Variable Block Size Motion Estimation
2010/12/15
The video coding standard H.264/AVC has adopted variable block size motion estimation to improve coding efficiency, which has brought heavy computation burden.The FFSBM (fast full search block matchin...
