搜索结果: 1-4 共查到“low area”相关记录4条 . 查询时间(0.078 秒)
A Low-Latency, Low-Area Hardware Oblivious RAM Controller
oblivous ram Path ORAM secure processors
2016/1/9
We build and evaluate Tiny ORAM, an Oblivious RAM prototype on FPGA. Oblivious RAM is a cryptographic primitive that completely obfuscates an application's data, access pattern and read/write behavior...
A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO
implementation / AES ECHO hash functions implementation SHA-3
2012/3/29
We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-$5$ and Virtex-$6$ FPGAs. Our architecture is built around a...
A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO
AES ECHO hash functions implementation SHA-3
2011/2/24
We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-$5$ and Virtex-$6$ FPGAs. Our architecture is built around a...
A Low-Area yet Performant FPGA Implementation of Shabal
implementation SHA-3 Shabal low area FPGA implementation
2010/7/13
In this paper, we present an efficient FPGA implementation of the SHA-3 hash function candidate Shabal. Targeted at the recent Xilinx Virtex-5 FPGA family, our design achieves a relatively high throug...
