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SIKE Round 2 Speed Record on ARM Cortex-M4
Post-quantum cryptography SIKE key encapsulation mechanism
2019/5/23
We present the first practical software implementation of Supersingular Isogeny Key Encapsulation (SIKE) round 2, targeting NIST’s 1, 2, and 5 security levels on 32-bit ARM Cortex-M4 microcontrollers....
Many crypto-algorithms, Deep-Learning, DSP compute on words larger than 8-bit. SCA attacks can easily be done on Boolean operations like XOR, AND, OR, and substitution operations like s-box, p-box or ...
Memory-Efficient High-Speed Implementation of Kyber on Cortex-M4
ARM Cortex-M4 number-theoretic transform lattice-based cryptography
2019/5/21
This paper presents an optimized software implementation of the module-lattice-based key-encapsulation mechanism Kyber for the ARM Cortex-M4 microcontroller. Kyber is one of the round-2 candidates in ...
Improving Speed of Dilithium’s Signing Procedure
Lattice based cryptography Dilithium digital signatures
2019/4/28
In this short note, we propose an optimization to improve the signing speed of Dilithium's signing procedure. Our optimization works by reducing the number of computations in the rejected iterations t...
A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES
NTRU lattice-based hardware
2019/4/1
In this paper, we present a high-speed constant time hardware implementation of NTRUEncrypt Short Vector Encryption Scheme (SVES), fully compliant with the IEEE 1363.1 Standard Specification for Publi...
Pushing the speed limit of constant-time discrete Gaussian sampling. A case study on Falcon
Post-quantum signature Falcon constant-time
2019/3/6
Sampling from discrete Gaussian distribution has applications in lattice-based post-quantum cryptography. Several efficient solutions have been proposed in recent years. However, making a Gaussian sam...
High-speed Side-channel-protected Encryption and Authentication in Hardware
AES Galois/Counter Mode (GCM) FPGA
2018/11/12
This paper describes two FPGA implementations for the encryption and authentication of data, based on the AES algorithm running in Galois/Counter mode (AES-GCM). Both architectures are protected again...
Faster multiplication in $\mathbb{Z}_{2^m}[x]$ on Cortex-M4 to speed up NIST PQC candidates
ARM Cortex-M4 Karatsuba Toom
2018/11/2
In this paper we optimize multiplication of polynomials in Z2m[x]Z2m[x] on the ARM Cortex-M4 microprocessor. We use these optimized multiplication routines to speed up the NIST post-quantum candidates...
Exploiting an HMAC-SHA-1 optimization to speed up PBKDF2
HMAC-SHA-1 Password-Based Key Derivation Function 2 Boyar-Peralta heuristic
2018/1/29
PBKDF2 [27] is a well-known password-based key derivation function. In order to slow attackers down, PBKDF2 introduces CPU-intensive operations based on an iterated pseudorandom function (in our case ...
Speed-ups and time-memory trade-offs for tuple lattice sieving
lattice-based cryptography shortest vector problem (SVP) nearest neighbor algorithms
2017/12/25
Our results extend and improve upon previous work of Bai-Laarhoven-Stehlé [ANTS'16] and Herold-Kirshanova [PKC'17], with better complexities for arbitrary tuple sizes and offering tunable time-memory ...
This paper presents software demonstrating that the 20-year-old NTRU cryptosystem is competitive with more recent lattice-based cryptosystems in terms of speed, key size, and ciphertext size. We prese...
High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves
Binary Edwards Generalized Hessian Curves
2017/2/20
In this paper high-speed hardware architectures of point multiplication based on Montgomery ladder algorithm for binary Edwards and generalized Hessian curves in Gaussian normal basis are presented. C...
High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m)
Cryptography Logical Effort Gaussian Normal Basis multiplication
2016/12/8
In this paper, by employing the logical effort technique an efficient and high-speed VLSI implementation of the digit-serial Gaussian normal basis multiplier is presented. It is constructed by using A...
FourQ on FPGA: New Hardware Speed Records for Elliptic Curve Cryptography over Large Prime Characteristic Fields
Elliptic curves FourQ FPGA
2016/6/6
We present fast and compact implementations of FourQ (ASIACRYPT
2015) on field-programmable gate arrays (FPGAs), and demonstrate,
for the first time, the high efficiency of this new elliptic curve o...
Efficient High-Speed WPA2 Brute Force Attacks using Scalable Low-Cost FPGA Clustering
FPGA WPA2 Security
2016/6/3
WPA2-Personal is widely used to protect Wi-Fi networks against illicit access. While attackers typically use GPUs to speed up the discovery of weak network passwords, attacking random passwords is con...
