搜索结果: 1-9 共查到“密码学 FPGA Implementation”相关记录9条 . 查询时间(0.048 秒)
Multi-core FPGA Implementation of ECC with Homogeneous Co-Z Coordinate Representation
ECC Co-Z Multi-Core
2016/12/9
Elliptic Curve Cryptography (ECC) is gaining popularity in recent years. Having short keys and short signatures in particular makes ECC likely to be adopted in numerous internet-of-things (IoT) device...
LED and PHOTON are new ultra-lightweight cryptographic algorithms aiming at resourceconstrained
devices. In this article, we describe three different hardware architectures of the LED and
PHOTON fam...
First Experimental Result of Power Analysis Attacks on a FPGA Implementation of LEA
power analysis attack LEA ARX
2016/1/5
The lightweight encryption algorithm (LEA) is a 128-bit block cipher introduced in 2013. It is based on Addition, rotation, XOR operations for 32-bit words. Because of its structure,it is useful for s...
A Preliminary FPGA Implementation and Analysis of Phatak’s Quotient-First Scaling Algorithm in the Reduced-Precision Residue Number System
Reduced-Precision Residue Number System Residue Number System (RNS) modular exponentiation
2016/1/5
We built and tested the first hardware implementation of Phatak’s Quotient-First Scaling (QFS) algorithm in the reduced-precision residue number system (RP-RNS). This algorithm is designed to expedite...
Enhanced FPGA Implementation of the Hummingbird Cryptographic Algorithm
Lightweight Cryptography FPGA Implementation Coprocessor Approach
2010/11/22
Hummingbird is a novel ultra-lightweight cryptographic algorithm aiming at resource-constrained devices. In this work, an enhanced hardware implementation of the Hummingbird cryptographic algorithm fo...
A Compact FPGA Implementation of the SHA-3 Candidate ECHO
Implementation the SHA-3 Candidate ECHO
2010/7/14
We propose a compact architecture of the SHA-3 candidate ECHO for the Virtex-5 FPGA family. Our architecture is built around a 8-bit datapath. We show that a careful organization of the chaining varia...
A Low-Area yet Performant FPGA Implementation of Shabal
implementation SHA-3 Shabal low area FPGA implementation
2010/7/13
In this paper, we present an efficient FPGA implementation of the SHA-3 hash function candidate Shabal. Targeted at the recent Xilinx Virtex-5 FPGA family, our design achieves a relatively high throug...
Parallel FPGA Implementation of RSA with Residue Number Systems— Can side-channel threats be avoided? —
RSA Residue Numbers Systems Side-Channels
2009/3/27
In this paper, we present a new parallel architecture to avoid
side-channel analyses such as: timing attack, simple/differential power
analysis, fault induction attack and simple/differential electr...
Electromagnetic Side Channels of an FPGA Implementation of AES
side channel attacks DEMA FPGA
2009/3/27
We show how to attack an FPGA implementation of AES
where all bytes are processed in parallel using differential electromagnetic
analysis. We first focus on exploiting local side channels to isolate...